AT25QL641 datasheet(34/77 Pages) DIALOG

tên linh kiện	AT25QL641

Giải thích chi tiết về linh kiện	64-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	77 Pages

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AT25QL641

DS-25QL641–130E–10/2018

Figure 7-25. Quad Page Program Instruction (QPI mode)

7.17

4 Kbyte Block Erase (20h)

The ‘Block Erase’ instruction is to erase the data of the selected block as being “1”. The instruction is used for 4K-byte

block. Prior to the ‘Block Erase’ instruction, the ‘Write Enable’ (06h) instruction must be issued. The instruction is

initiated by driving the CS pin low and shifting the instruction code “20h” followed a 24-bit block address (A23-A0) as

shown in Figure 7-26 and Figure 7-27. The CS pin must go high after the eighth bit of the last byte has been latched in,

otherwise the Block Erase instruction is not executed. After CS goes high, the self-timed ‘Block Erase’ instruction

commences for a time duration of t

SE (see Table 8-7, AC Electrical Characteristics).

While the block erase operation is in progress, the ‘Read Status Register’ (05h) instruction may still be accessed for

checking the status of the BUSY bit. The BUSY bit is a 1 during the block erase operation and becomes a 0 when the

cycle is finished and the device is ready to accept other instructions again. When the BUSY bit is asserted, the Write

Enable Latch (WEL) bit in the Status Register is cleared to 0.

Figure 7-26. Block Erase Instruction (SPI Mode)

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