AT25QL641 datasheet(32/77 Pages) DIALOG

tên linh kiện	AT25QL641

Giải thích chi tiết về linh kiện	64-Mbit, 1.7V Minimum SPI Serial Flash Memory with Dual I/O, Quad I/O and QPI Support

PDF	77 Pages

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32 / 77 page

AT25QL641

DS-25QL641–130E–10/2018

the number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device the

addressing wraps around to the beginning of the page and overwrites previously sent data.

The CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done, the Page

Program instruction is not executed. After CS is driven high, the self-timed ‘Page Program’ instruction commences for

a time duration of tPP (see Table 8-7, AC Electrical Characteristics). While the page program operation is in progress, the

‘Read Status Register’ instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1

during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other

instructions again. When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in the Status Register is cleared to

Figure 7-22. Page Program Instruction (SPI Mode)

Figure 7-23. Page Program Instruction (QPI Mode)

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