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AT25QL641 bảng dữ liệu(PDF) 21 Page - Dialog Semiconductor |
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AT25QL641 bảng dữ liệu(HTML) 21 Page - Dialog Semiconductor |
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21 / 77 page  20 AT25QL641 DS-25QL641–130E–10/2018 7.5 Read Status Register-1 (05h) and Read Status Register-2 (35h) The Read Status Register instructions are to read the Status register. The Read Status Register instructions can be executed at any time (even in the Program/Erase/Write Status Register and Write Security Register conditions). It is recommended to check the BUSY bit before sending a new instruction when a Program, Erase, Write Status Register or Write Status Register operation is in progress. The instruction is entered by driving CS low and sending the instruction code “05h” for Status Register-1 or “35h” for Status Register-2 into the SI pin on the rising edge of SCK. The status register bits are then shifted out on the SO pin at the falling edge of SCK with most significant bit (MSB) first as shown in (Figure 7-4 and Figure 7-5). The Status Register can be read continuously. The instruction is completed by driving CS high. Figure 7-4. Read Status Register Instruction (SPI Mode) Figure 7-5. Read Status Register Instruction (QPI Mode) 7.6 Write Status Register (01h) The Write Status Register instruction is u s e d to write only t h e non-volatile Status Register-1 bit SRP0, and Status Register-2 bits QE and SRP1. All other Status Register bit locations are read-only and are not affected by the Write Status Register instruction. A Write Enable instruction must previously have been issued prior to setting Write Status Register Instruction (Status Register bit WEL must equal 1). Once the write is enabled, the instruction is entered by driving CS low, sending the instruction code, and then writing the status register data byte as illustrated in Figure 7-6 and Figure 7-7. |
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