TMS320F28375DPZP datasheet(200/226 Pages) TI

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9.12 Timers

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The

timers have a 32-bit count-down register that generates an interrupt when the counter reaches zero. The counter

is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it

is automatically reloaded with a 32-bit period value.

CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and is

connected to INT13 of the CPU. CPU-Timer 2 is reserved for TI-RTOS. It is connected to INT14 of the CPU. If

TI-RTOS is not being used, CPU-Timer 2 is available for general use.

CPU-Timer 2 can be clocked by any one of the following:

• SYSCLK (default)

• Internal zero-pin oscillator 1 (INTOSC1)

• Internal zero-pin oscillator 2 (INTOSC2)

• X1 (XTAL)

• AUXPLLCLK

9.13 Nonmaskable Interrupt With Watchdog Timer (NMIWD)

The NMIWD module is used to handle system-level errors. There is an NMIWD module for each CPU. The

conditions monitored are:

• Missing system clock due to oscillator failure

• Uncorrectable ECC error on CPU access to flash memory

• Uncorrectable ECC error on CPU, CLA, or DMA access to RAM

• Vector fetch error on the other CPU

• CPU1 only: Watchdog or NMI watchdog reset on CPU2

If the CPU does not respond to the latched error condition, then the NMI watchdog will trigger a reset after a

programmable time interval. The default time is 65536 SYSCLK cycles.

TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

www.ti.com

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TMS320F28375DPZP bảng dữ liệu(PDF) 200 Page - Texas Instruments