TMS320F28375DPZP datasheet(185/226 Pages) TI

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9.3.5 Memory Types

Table 9-6 provides more information about each memory type.

Table 9-6. Memory Types

MEMORY TYPE

ECC-CAPABLE

PARITY

SECURITY

HIBERNATE

RETENTION

ACCESS

PROTECTION

M0, M1

Yes

–

Yes

–

D0, D1

Yes

–

Yes

–

Yes

LSx

–

Yes

–

Yes

GSx

–

Yes

–

Yes

CPU/CLA MSGRAM

–

Yes

–

Yes

Boot ROM

–

N/A

–

Secure ROM

–

Yes

N/A

–

Flash

Yes

–

Yes

N/A

User-configurable DCSM OTP

Yes

–

Yes

N/A

9.3.5.1 Dedicated RAM (Mx and Dx RAM)

The CPU subsystem has four dedicated ECC-capable RAM blocks: M0, M1, D0, and D1. M0/M1 memories are

small nonsecure blocks that are tightly coupled with the CPU (that is, only the CPU has access to them). D0/D1

memories are secure blocks and also have the access-protection feature (CPU write/CPU fetch protection).

9.3.5.2 Local Shared RAM (LSx RAM)

RAM blocks which are dedicated to each subsystem and are accessible to its CPU and CLA only, are called

local shared RAMs (LSx RAMs).

All LSx RAM blocks have parity. These memories are secure and have the access protection (CPU write/CPU

fetch) feature.

By default, these memories are dedicated to the CPU only, and the user could choose to share these memories

with the CLA by configuring the MSEL_LSx bit field in the LSxMSEL registers appropriately.

Table 9-7 shows the master access for the LSx RAM.

Table 9-7. Master Access for LSx RAM

(With Assumption That all Other Access Protections are Disabled)

MSEL_LSx

CLAPGM_LSx

CPU ALLOWED ACCESS CLA ALLOWED ACCESS

COMMENT

All

–

LSx memory is configured

as CPU dedicated RAM.

All

Data Read

Data Write

LSx memory is shared

between CPU and CLA1.

Emulation Read

Emulation Write

Fetch Only

LSx memory is CLA1

program memory.

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TMS320F28379D, TMS320F28379D-Q1, TMS320F28378D, TMS320F28377D

TMS320F28377D-Q1, TMS320F28376D, TMS320F28375D, TMS320F28374D

SPRS880O – DECEMBER 2013 – REVISED FEBRUARY 2021

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