ADRF6755ACPZ-R7 datasheet(35/48 Pages) AD

35 / 48 page

Data Sheet

ADRF6755

Rev. B | Page 35 of 48

SUGGESTED POWER-UP SEQUENCE

INITIAL REGISTER WRITE SEQUENCE

After applying power to the part, perform the initial register write

sequence that follows. Note that Register CR33, Register CR32, and

registers should be written to on power-up. Refer to the Register

Map section for more details on all registers.

1. Write 0x00 to Register CR30. Set the attenuator to 0 dB gain.

2. Write 0x80 to Register CR29. The modulator is powered

down. The modulator is powered down by default to ensure

that no spurious signals can occur on the RF output when

the PLL is carrying out its first acquisition. The modulator

should be powered up only when the PLL is locked.

3. Write 0x0X to Register CR28. RFDIV depends on the value

of the LO frequency to be used and is set according to

Table 6. Note that Register CR28, Bit 3, is set to 1.

4. Write 0xX0 to Register CR27. Bit 4 depends on the LO

frequency to be used and is set according to Table 6.

5. Write 0x00 to Register CR26. Reserved register.

6. Write 0x64 to Register CR25, the autocalibration timer.

This setting applies for PFD = 40 MHz. For other PFDs,

refer to Equation 3 in the VCO Autocalibration section.

7. Write 0x18 to Register CR24. Enable autocalibration.

8. Write 0x70 to Register CR23. Enable the lock detector and

choose the recommended lock detect timing. This setting

applies to PFD = 40 MHz. For other PFDs, refer to the

Lock Detect (LDET) section in the Program Modes

section.

9. Write 0x80 to Register CR22. Reserved register.

10. Write 0x00 to Register CR21. Reserved register.

11. Write 0x00 to Register CR20. Reserved register.

12. Write 0x80 to Register CR19. Reserved register.

13. Write 0x60 to Register CR18. Reserved register.

14. Write 0x00 to Register CR17. Reserved register.

15. Write 0x00 to Register CR16. Reserved register.

16. Write 0x00 to Register CR15. Reserved register.

17. Write 0x80 to Register CR14. Stop LO when TXDIS = 1.

18. Write 0xE8 to Register CR13. This setting applies to PFD =

40 MHz. For other PFDs, refer to the Lock Detect (LDET)

section in the Program Modes section.

19. Write 0x18 to Register CR12. Power up the PLL.

20. Write 0x00 to Register CR11. Reserved register.

21. Write to Register CR10. Refer to the Reference Input Path

section, in particular Equation 1.

22. Write 0xF0 to Register CR9. With the recommended loop

filter component values and RSET = 4.7 kΩ, as shown in

Figure 70, the charge pump current is set to 5 mA for a

loop bandwidth of 100 kHz.

23. Write 0x00 to Register CR8. Reserved register.

24. Write 0x0X to Register CR7. Set according to Equation 2 in

the Theory of Operation section. Also, set the MUXOUT

pin to tristate.

25. Write 0xXX to Register CR6. Set according to Equation 2

in the Theory of Operation section.

26. Write to Register CR5. Refer to the Reference Input Path

section, in particular Equation 1.

27. Write 0x01 to Register CR4. Reserved register.

28. Write 0000010X binary to Register CR3. Set according to

Equation 2 in the Theory of Operation section.

29. Write 0xXX to Register CR2. Set according to Equation 2

in the Theory of Operation section.

30. Write 0xXX to Register CR1. Set according to Equation 2

in the Theory of Operation section.

31. Write 0xXX to Register CR0. Set according to Equation 2

in the Theory of Operation section. Register CR0 must be

the last register written for all the double-buffered bit

writes to take effect.

32. Write to Register CR27, setting Bit 4 according to Table 6.

33. Monitor the LDET output or wait 170 μs to ensure that the

PLL is locked.

34. Write 0x81 to Register CR29. Power up the modulator. The

write to Register CR29 does not need to be followed by a write

to Register CR0 because this register is not double-buffered.

Example—Changing the LO Frequency

Following is an example of how to change the LO frequency

after the initialization sequence. Using an example in which

the PLL is locked to 2000 MHz, the following conditions apply:

•

fPFD = 40 MHz (assumed)

•

Divide ratio N = 50; therefore, INT = 50 decimal and

FRAC = 0

•

RFDIVIDER = divide-by-1. See Table 6.

The INT registers contain the following values:

The FRAC registers contain the following values:

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