ADRF6755ACPZ-R7 datasheet(30/48 Pages) AD

30 / 48 page

ADRF6755

Data Sheet

Rev. B | Page 30 of 48

Lock Detect (LDET)

Lock detect is enabled by setting Register CR23, Bit 4, to 1. The

lock detect circuit is based on monitoring the up/down pulses

from the PFD. As acquisition proceeds, the width of these

pulses reduces until they are less than a target width (set by

CR23[2]). At this point, a count of the number of successive

PFD cycles is initiated, where the width of the up/down pulses

remains less that the target width. When this count reaches a

target count (set by CR13[6] and CR23[3]), LDET is set. The

truth table for declaring LDET is given in Table 7.

Table 7. Declaring LDET

LDCount1

CR13[6]

LDCount0

CR23[3]

Number of PFD Cycles to

Declare LDET

2048

3072

4096

16,384

The appropriate setting to use depends on the PFD frequency as

well as the desired accuracy when LDET is declared. The LDET

setting does not affect the acquisition time of the PLL. It only

affects the time at which LDET goes high.

VCO Autocalibration

The VCO uses an autocalibration technique to select the correct

VCO and band, as explained in the Autocalibration section.

enabled. For normal operation, autocalibration must be enabled.

However, if using cumulative frequency steps of 100 kHz/2RFDIV

or less, autocalibration can be disabled by setting this bit to 1

and then a new acquisition is initiated by writing to Register CR0.

Attenuator

The attenuator can be programmed from 0 dB to 47 dB in steps

of 1 dB. Control is through Register CR30, Bits[5:0].

Revision Readback

The revision of the silicon die can be read back via Register CR33.

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