PRT2011DAF4A datasheet(16/112 Pages) NXP

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i.MX RT1064 Crossover Processors Data Sheet for Consumer Products, Rev. 2, 08/2020

NXP Semiconductors

Modules List

3.1

Special signal considerations

Table 3 lists special signal considerations for the i.MX RT1064 processors. The signal names are listed in

alphabetical order.

The package contact assignments can be found in Section 7, Package information and contact

assignments.” Signal descriptions are provided in the i.MX RT1064 Reference Manual

(IMXRT1064RM).

Table 3. Special signal considerations

Signal Name

Remarks

CCM_CLK1_P/

CCM_CLK1_N

One general purpose differential high speed clock Input/output (LVDS I/O) is provided.

It can be used:

• To feed external reference clock to the PLLs and further to the modules inside SoC.

• To output internal SoC clock to be used outside the SoC as either reference clock or as a

functional clock for peripherals.

See the i.MX RT1064 Reference Manual (IMXRT1064RM) for details on the respective clock trees.

Alternatively one may use single ended signal to drive CLK1_P input. In this case corresponding

CLK1_N input should be tied to the constant voltage level equal 1/2 of the input signal swing.

Termination should be provided in case of high frequency signals.

After initialization, the CLK1 input/output can be disabled (if not used). If unused either or both of

the CLK1_N/P pairs may remain unconnected.

DCDC_PSWITCH

PAD is in DCDC_IN domain and connected the ground to bypass DCDC.

To enable DCDC function, assert to DCDC_IN with at least 1ms delay for DCDC_IN rising edge.

RTC_XTALI/RTC_XTALO If the user wishes to configure RTC_XTALI and RTC_XTALO as an RTC oscillator, a 32.768 kHz

crystal, (

100 k ESR, 10 pF load) should be connected between RTC_XTALI and RTC_XTALO.

Keep in mind the capacitors implemented on either side of the crystal are about twice the crystal

load capacitor. To hit the exact oscillation frequency, the board capacitors need to be reduced to

account for board and chip parasitics. The integrated oscillation amplifier is self biasing, but

relatively weak. Care must be taken to limit parasitic leakage from RTC_XTALI and RTC_XTALO

to either power or ground (>100 M

). This will debias the amplifier and cause a reduction of startup

margin. Typically RTC_XTALI and RTC_XTALO should bias to approximately 0.5 V.

If it is desired to feed an external low frequency clock into RTC_XTALI the RTC_XTALO pin must

remain unconnected or driven with a complimentary signal. The logic level of this forcing clock

should not exceed VDD_SNVS_CAP level and the frequency should be <100 kHz under typical

conditions.

In case when high accuracy real time clock are not required system may use internal low frequency

ring oscillator. It is recommended to connect RTC_XTALI to GND and keep RTC_XTALO

unconnected.

XTALI/XTALO

A 24.0 MHz crystal should be connected between XTALI and XTALO.

The crystal must be rated for a maximum drive level of 250

W. An ESR (equivalent series

resistance) of typical 80

 is recommended. NXP SDK software requires 24 MHz on

XTALI/XTALO.

The crystal can be eliminated if an external 24 MHz oscillator is available in the system. In this

case, XTALO must be directly driven by the external oscillator and XTALI mounted with 18 pF

capacitor. The logic level of this forcing clock cannot exceed NVCC_PLL level.

If this clock is used as a reference for USB, then there are strict frequency tolerance and jitter

requirements. See OSC24M chapter and relevant interface specifications chapters for details.

GPANAIO

This signal is reserved for NXP manufacturing use only. This output must remain unconnected.

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