AT90PWM2 datasheet(28/365 Pages) ATMEL

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AT90PWM2/3

4317B–AVR–02/05

I/O Memory

The I/O space definition of the AT90PWM2/3 is shown in “Register Summary” on page

348.

All AT90PWM2/3 I/Os and peripherals are placed in the I/O space. All I/O locations may

be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data

between the 32 general purpose working registers and the I/O space. I/O registers

within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI

instructions. In these registers, the value of single bits can be checked by using the

SBIS and SBIC instructions. Refer to the instruction set section for more details. When

using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be

used. When addressing I/O registers as data space using LD and ST instructions, 0x20

must be added to these addresses. The AT90PWM2/3 is a complex microcontroller with

more peripheral units than can be supported within the 64 location reserved in Opcode

for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM,

only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that, unlike

most other AVR’s, the CBI and SBI instructions will only operate on the specified bit, and

can therefore be used on registers containing such status flags. The CBI and SBI

instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

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