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AT90PWM2 bảng dữ liệu(PDF) 85 Page - ATMEL Corporation |
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AT90PWM2 bảng dữ liệu(HTML) 85 Page - ATMEL Corporation |
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85 / 365 page  85 AT90PWM2/3 4317B–AVR–02/05 the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari- ation of the system clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_I/O/2.5. An external clock source can not be prescaled. Figure 30. Prescaler for Timer/Counter0 and Timer/Counter1(1) Note: 1. The synchronization logic on the input pins ( Tn/T0) is shown in Figure 29. General Timer/Counter Control Register – GTCCR • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value that is written to the PSRSYNC bit is kept, hence keeping the corre- sponding prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. When the TSM bit is written to zero, the PSRSYNC bit is cleared by hardware, and the Timer/Counters start counting simultaneously. PSRSYNC Clear clk T1 clk T0 T1 T0 clk I/O Synchronization Synchronization Bit 7 6 5 4 3 2 1 0 TSM ICPSEL1 – – – – – PSRSYNC GTCCR Read/Write R/W R/W R R R R R R/W Initial Value 0 0 0 0 0 0 0 0 |
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