AT90PWM2 datasheet(93/365 Pages) ATMEL

93 / 365 page

AT90PWM2/3

4317B–AVR–02/05

match. The counter will then have to count to its maximum value (0xFF) and wrap

around starting at 0x00 before the compare match can occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle

its logical level on each compare match by setting the Compare Output mode bits to tog-

gle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the

data direction for the pin is set to output. The waveform generated will have a maximum

frequency of f

OC0 = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency

is defined by the following equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle

that the counter counts from MAX to 0x00.

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high

frequency PWM waveform generation option. The fast PWM differs from the other PWM

option by its single-slope operation. The counter counts from BOTTOM to TOP then

restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when

WGM2:0 = 7. In non-inverting Compare Output mode, the Output Compare (OC0x) is

cleared on the compare match between TCNT0 and OCR0x, and set at BOTTOM. In

inverting Compare Output mode, the output is set on compare match and cleared at

BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM

mode can be twice as high as the phase correct PWM mode that use dual-slope opera-

tion. This high frequency makes the fast PWM mode well suited for power regulation,

rectification, and DAC applications. High frequency allows physically small sized exter-

nal components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP

value. The counter is then cleared at the following timer clock cycle. The timing diagram

for the fast PWM mode is shown in Figure 36. The TCNT0 value is in the timing diagram

shown as a histogram for illustrating the single-slope operation. The diagram includes

non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0

slopes represent compare matches between OCR0x and TCNT0.

Figure 36. Fast PWM Mode, Timing Diagram

OC nx

clk_I/O

2 N

OCRnx

()

⋅⋅

--------------------------------------------------

TCNTn

OCRnx Update and

TOVn Interrupt Flag Set

Period

OCn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

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