AT90PWM2 datasheet(77/365 Pages) ATMEL

77 / 365 page

AT90PWM2/3

4317B–AVR–02/05

CLKO, Divided System Clock: The divided system clock can be output on this pin. The

divided system clock will be output if the CKOUT Fuse is programmed, regardless of the

PORTD1 and DDD1 settings. It will also be output during reset.

• PSCOUT00/XCK/SS_A – Bit 0

PSCOUT00: Output 0 of PSC 0.

XCK, USART External clock. The Data Direction Register (DDD0) controls whether the

clock is output (DDD0 set) or input (DDD0 cleared). The XCK0 pin is active only when

the USART operates in Synchronous mode.

SS_A: Slave Port Select input. When the SPI is enabled as a slave, this pin is config-

ured as an input regardless of the setting of DDD0. As a slave, the SPI is activated when

this pin is driven low. When the SPI is enabled as a master, the data direction of this pin

is controlled by DDD0. When the pin is forced to be an input, the pull-up can still be con-

trolled by the PORTD0 bit.

Table 31 and Table 32 relates the alternate functions of Port D to the overriding signals

shown in Figure 28 on page 68.

Table 31. Overriding Signals for Alternate Functions PD7..PD4

Signal Name

PD7

PD6

PD5/

PD4/

PUOE

––

–

PUOV

––

–

DDOE

––

–

DDOV

––

–

PVOE

––

–

PVOV

––

–

PTOE

––

–

DIEOE

––

–

DIEOV

––

–

––

–

AIO

––

–

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