AT90PWM2 datasheet(90/365 Pages) ATMEL

90 / 365 page

AT90PWM2/3

4317B–AVR–02/05

Figure 33. Output Compare Unit, Block Diagram

The OCR0x Registers are double buffered when using any of the Pulse Width Modula-

tion (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of

operation, the double buffering is disabled. The double buffering synchronizes the

update of the OCR0x Compare Registers to either top or bottom of the counting

sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical

PWM pulses, thereby making the output glitch-free.

The OCR0x Register access may seem complex, but this is not case. When the double

buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double

buffering is disabled the CPU will access the OCR0x directly.

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing compare

match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be

updated as if a real compare match had occurred (the COM0x1:0 bits settings define

whether the OC0x pin is set, cleared or toggled).

Compare Match Blocking by

TCNT0 Write

All CPU write operations to the TCNT0 Register will block any compare match that

occur in the next timer clock cycle, even when the timer is stopped. This feature allows

OCR0x to be initialized to the same value as TCNT0 without triggering an interrupt when

the Timer/Counter clock is enabled.

Using the Output Compare

Unit

Since writing TCNT0 in any mode of operation will block all compare matches for one

timer clock cycle, there are risks involved when changing TCNT0 when using the Output

Compare Unit, independently of whether the Timer/Counter is running or not. If the

value written to TCNT0 equals the OCR0x value, the compare match will be missed,

resulting in incorrect waveform generation. Similarly, do not write the TCNT0 value

equal to BOTTOM when the counter is downcounting.

The setup of the OC0x should be performed before setting the Data Direction Register

for the port pin to output. The easiest way of setting the OC0x value is to use the Force

Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their

values even when changing between Waveform Generation modes.

OCFnx (Int.Req.)

= (8-bit Comparator )

OCRnx

OCnx

DATA BUS

TCNTn

WGMn1:0

Waveform Generator

top

FOCn

COMnx1:0

bottom

AT90PWM2 bảng dữ liệu(PDF) 90 Page - ATMEL Corporation

AT90PWM2 bảng dữ liệu(HTML) 90 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL