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AT90PWM2 bảng dữ liệu(PDF) 99 Page - ATMEL Corporation

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Giải thích chi tiết về linh kiện  8-bit Microcontroller with 8K Bytes In-System Programmable Flash
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99
AT90PWM2/3
4317B–AVR–02/05
Table 42 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to fast
PWM mode.
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 93 for more details.
Table 43 shows the COM0B1:0 bit functionality when the WGM02:0 bits are set to
phase correct PWM mode.
Note:
1. A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case,
the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Cor-
rect PWM Mode” on page 94 for more details.
• Bits 3, 2 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM2/3 and will always read as zero.
• Bits 1:0 – WGM01:0: Waveform Generation Mode
Combined with the WGM02 bit found in the TCCR0B Register, these bits control the
counting sequence of the counter, the source for maximum (TOP) counter value, and
what type of waveform generation to be used, see Table 44. Modes of operation sup-
ported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare
Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (see
“Modes of Operation” on page 92).
Table 42. Compare Output Mode, Fast PWM Mode(1)
COM0B1
COM0B0
Description
0
0
Normal port operation, OC0B disconnected.
01
Reserved
1
0
Clear OC0B on Compare Match, set OC0B at TOP
1
1
Set OC0B on Compare Match, clear OC0B at TOP
Table 43. Compare Output Mode, Phase Correct PWM Mode
(1)
COM0B1
COM0B0
Description
0
0
Normal port operation, OC0B disconnected.
01
Reserved
1
0
Clear OC0B on Compare Match when up-counting. Set OC0B on
Compare Match when down-counting.
1
1
Set OC0B on Compare Match when up-counting. Clear OC0B on
Compare Match when down-counting.
Table 44. Waveform Generation Mode Bit Description
Mode
WGM02
WGM01
WGM00
Timer/Count
er Mode of
Operation
TOP
Update of
OCRx at
TOV Flag
Set on
(1)(2)
0
0
0
0
Normal
0xFF
Immediate
MAX
1
0
0
1
PWM, Phase
Correct
0xFF
TOP
BOTTOM
2
0
1
0
CTC
OCRA
Immediate
MAX
3
011
Fast PWM
0xFF
TOP
MAX



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