AT90PWM2 datasheet(96/365 Pages) ATMEL

96 / 365 page

AT90PWM2/3

4317B–AVR–02/05

Match. To ensure symmetry around BOTTOM the OCnx value at MAX must

correspond to the result of an up-counting Compare Match.

•

The timer starts counting from a value higher than the one in OCRnx, and for that

reason misses the Compare Match and hence the OCnx change that would have

happened on the way up.

Timer/Counter Timing

Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

T0) is therefore

shown as a clock enable signal in the following figures. The figures include information

on when interrupt flags are set. Figure 38 contains timing data for basic Timer/Counter

operation. The figure shows the count sequence close to the MAX value in all modes

other than phase correct PWM mode.

Figure 38. Timer/Counter Timing Diagram, no Prescaling

Figure 39 shows the same timing data, but with the prescaler enabled.

Figure 39. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O/8)

Figure 40 shows the setting of OCF0B in all modes and OCF0A in all modes except

CTC mode and PWM mode, where OCR0A is TOP.

Figure 40. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f

clk_I/O/8)

clk

(clk

I/O/1)

TOVn

clk

I/O

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

TOVn

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

clk

I/O

clk

(clk

I/O/8)

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