AT90PWM2 datasheet(269/365 Pages) ATMEL

269 / 365 page

269

AT90PWM2/3

4317B–AVR–02/05

DAC Register Description

The DAC is controlled via three dedicated registers:

•

The DACON register which is used for DAC configuration

•

DACH and DACL which are used to set the value to be converted.

Digital to Analog Conversion

Control Register – DACON

• Bit 7 – DAATE: DAC Auto Trigger Enable bit

Set this bit to update the DAC input value on the positive edge of the trigger signal

selected with the DACTS2-0 bit in DACON register.

Clear it to automatically update the DAC input when a value is written on DACH register.

• Bit 6:4 – DATS2, DATS1, DATS0: DAC Trigger Selection bits

These bits are only necessary in case the DAC works in auto trigger mode. It means if

DAATE bit is set.

In accordance with the Table 108, these 3 bits select the interrupt event which will gen-

erate the update of the DAC input values. The update will be generated by the rising

edge of the selected interrupt flag whether the interrupt is enabled or not.

• Bit 2 – DALA: Digital to Analog Left Adjust

Set this bit to left adjust the DAC input data.

Clear it to right adjust the DAC input data.

The DALA bit affects the configuration of the DAC data registers. Changing this bit

affects the DAC output on the next DACH writing.

• Bit 1 – DAOE: Digital to Analog Output Enable bit

Set this bit to output the conversion result on AD2,

Clear it to use the DAC internally.

• Bit 0 – DAEN: Digital to Analog Enable bit

Set this bit to enable the DAC,

Clear it to disable the DAC.

Bit

DAATE

DATS2

DATS1

DATS0

DALA

DAOE

DAEN

DACON

Read/Write

R/W

Initial Value

Table 108. DAC Auto Trigger source selection

DATS2

DATS1

DATS0

Description

Analog comparator 0

Analog comparator 1

External Interrupt Request 0

Timer/Counter0 Compare Match

Timer/Counter0 Overflow

Timer/Counter1 Compare Match B

Timer/Counter1 Overflow

Timer/Counter1 Capture Event

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