AT90PWM2 datasheet(258/365 Pages) ATMEL

258 / 365 page

258

AT90PWM2/3

4317B–AVR–02/05

If these bits are changed during a conversion, the change will not take effect until this

conversion is complete (it means while the ADIF bit in ADCSRA register is set).

ADC Control and Status

• Bit 7 – ADEN: ADC Enable Bit

Set this bit to enable the ADC.

Clear this bit to disable the ADC.

Clearing this bit while a conversion is running will take effect at the end of the

conversion.

• Bit 6– ADSC: ADC Start Conversion Bit

Set this bit to start a conversion in single conversion mode or to start the first conversion

in free running mode.

Cleared by hardware when the conversion is complete. Writing this bit to zero has no

effect.

The first conversion performs the initialization of the ADC.

• Bit 5 – ADATE: ADC Auto trigger Enable Bit

Set this bit to enable the auto triggering mode of the ADC.

Clear it to return in single conversion mode.

In auto trigger mode the trigger source is selected by the ADTS bits in the ADCSRB reg-

ister. See Table 103 on page 259.

• Bit 4– ADIF: ADC Interrupt Flag

Set by hardware as soon as a conversion is complete and the Data register are updated

with the conversion result.

Cleared by hardware when executing the corresponding interrupt handling vector.

Alternatively, ADIF can be cleared by writing it to logical one.

• Bit 3– ADIE: ADC Interrupt Enable Bit

ADC5

ADC6

ADC7

ADC8

ADC9

ADC10

AMP0

AMP1 (- is ADC8, + is ADC9)

Reserved

Bandgap

GND

Table 101. ADC Input Channel Selection

MUX3

MUX2

MUX1

MUX0

Description

Bit

ADEN

ADSC

ADATE

ADIF

ADIE

ADPS2

ADPS1

ADPS0

ADCSRA

Read/Write

R/W

Initial Value

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