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AT90PWM2 bảng dữ liệu(PDF) 237 Page - ATMEL Corporation |
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AT90PWM2 bảng dữ liệu(HTML) 237 Page - ATMEL Corporation |
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237 / 365 page  237 AT90PWM2/3 4317B–AVR–02/05 Figure 114. Analog Comparator Block Diagram(1)(2) Notes: 1. ADC multiplexer output: see Table 101 on page 257. 2. Refer to Figure 1 on page 3 and for Analog Comparator pin placement. 3. The voltage on Vref is defined in Table 100.ADC Voltage Reference Selection257 Analog Comparator Register Description Each analog comparator has its own control register. A dedicated register has been designed to consign the outputs and the flags of the 3 analog comparators. Analog Comparator 0 Control Register – AC0CON • Bit 7– AC0EN: Analog Comparator 0 Enable Bit Set this bit to enable the analog comparator 0. Clear this bit to disable the analog comparator 0. • Bit 6– AC0IE: Analog Comparator 0 Interrupt Enable bit Set this bit to enable the analog comparator 0 interrupt. Clear this bit to disable the analog comparator 0 interrupt. • Bit 5, 4– AC0IS1, AC0IS0: Analog Comparator 0 Interrupt Select bit + - Interrupt Sensitivity Control Analog Comparator 0 Interrupt AC0IE AC0IF AC0O AC0IS1 AC0IS0 + - Interrupt Sensitivity Control Analog Comparator 1 Interrupt AC1IE T1 Capture Trigger AC1ICE AC1IF AC1O AC1IS1 AC1IS0 + - Interrupt Sensitivity Control Analog Comparator 2 Interrupt AC0IE AC2IF AC2O AC2IS1 AC2IS0 ACMP0 ACMP1 ACMP2 AC2EN /3.20 /2.13 /1.60 /6.40 ACMPM Vref DAC AC0M 2 1 0 DAC Result AC1EN AC0EN AC1M 2 1 0 AC2M 2 1 0 Internal 2.56V Reference REFS0 REFS1 Aref AVcc DACEN CLK I/O CLK I/O CLK I/O (/2) (/2) (/2) Bit 7 65 43 21 0 AC0EN AC0IE AC0IS1 AC0IS0 - AC0M2 AC0M1 AC0M0 AC0CON Read/Write R/W R/W R/W R/W - R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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