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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AT90PWM2 bảng dữ liệu(PDF) 230 Page - ATMEL Corporation |
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AT90PWM2 bảng dữ liệu(HTML) 230 Page - ATMEL Corporation |
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230 / 365 page  230 AT90PWM2/3 4317B–AVR–02/05 Parity Checker The parity checker of the EUSART is available only when data bits are level encoded and behaves as is USART mode (See Parity checker of the USART). OverRun The Data OverRun (DOR bit of USCRA) flag indicates data loss due to a receiver buffer full condition. This flag operates as in USART mode (See USART section). EUSART Registers Description USART I/O Data Register – UDR • Bit 7:0 – RxB7:0: Receive Data Buffer (read access) • Bit 7:0 – TxB7:0: Transmit Data Buffer (write access) This register is common to the USART and EUSART interfaces for Transmit Data Buffer Register and Receive Data Buffer Register. See description for UDR register in USART. EUSART I/O Data Register – EUDR • Bit 7:0 – RxB15:8: Receive Data Buffer (read access) • Bit 7:0 – TxB15:8: Transmit Data Buffer (write access) This register provide an extension to the UDR register when EUSART is used with more than 8 bits. UDR/EUDR data access with character size up to 8 bits When the EUSART is used with 8 or less bits, only the UDR register is used for dta access. UDR/EUDR data access with 9 bits per character When the EUSART is used with 9 bits character, the behavior is different of the standart USART mode, the UDR register is used in combinaison with the first bit of EUDR (EUDR:0) for data access, the RxB8/TxB8 bit is not used. Figure 111. 9 bits communication data access Bit 7 65432 1 0 RXB[7:0] UDR (Read) TXB[7:0] UDR (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65432 1 0 RXB[15:8] EUDR (Read) TXB[15:8] EUDR (Write) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 87 0 Data 8:0 UDR EUDR |
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