AT90PWM2 datasheet(150/365 Pages) ATMEL

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AT90PWM2/3

4317A-3–AVR–02/05

Figure 73. Burst Generation

PSC Input Configuration

The PSC Input Configuration is done by programming bits in configuration registers.

Filter Enable

If the “Filter Enable” bit is set, a digital filter of 4 cycles is inserted before evaluation of

the signal. The disable of this function is mainly needed for prescaled PSC clock

sources, where the noise cancellation gives too high latency.

Important: If the digital filter is active, the level sensitivity is true also with a disturbed

PSC clock to deactivate the outputs (emergency protection of external component).

Likewise when used as fault input, PSCn Input A or Input B have to go through PSC to

act on PSCOUTn0/1/2/3 output. This way needs that CLK

PSC is running. So thanks to

PSC Asynchronous Output Control bit (PAOCnA/B), PSCnIN0/1 input can desactivate

directly the PSC output. Notice that in this case, input is still taken into account as usu-

ally by Input Module System as soon as CLK

PSC is running.

PSC Input Filterring

Signal Polarity

One can select the active edge (edge modes) or the active level (level modes) See

PELEVnx bit description in Section “PSC n Input A Control Register – PFRCnA”,

page 176.

If PELEVnx bit set, the significant edge of PSCn Input A or B is rising (edge modes) or

the active level is high (level modes) and vice versa for unset/falling/low

OFF

PSCOUTn0

PSCOUTn1

PSCn Input A

(high level)

PSCn Input A

(low level)

BURST

Digital

Filter

4 x CLK

PSC Input

Module X

Ouput

Stage

PSCOUTnX

PSCn Input A or B

CLKPSC

PSC

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