UPD17P136ACT datasheet(96/292 Pages) NEC

96 / 292 page

CHAPTER 10

DATA BUFFER (DBF)

The data buffer consists of four nibbles allocated in addresses 0CH to 0FH in BANK0.

The data buffer acts as a data storage area for the CPU peripheral circuit (address register, serial interface, timer

0, timer1, basic internal timer, and A/D converter) through use of the GET and PUT instructions. It also acts as data

storage used for receiving and transferring data. By using the MOVT, DBF, and @AR instructions, fixed data in

program memory can be read into the data buffer.

10.1 DATA BUFFER CONFIGURATION

Figure 10-1 shows the allocation of the data buffer in data memory.

As shown in Figure 10-1, the data buffer is allocated in address locations 0CH to 0FH in BANK0 and consists of

a total of 16 bits (4

× 4 bits).

Figure 10-1. Allocation of the Data Buffer

Figure 10-2 shows the configuration of the data buffer. As shown in Figure 10-2, the data buffer is made up of

16 bits with its LSB in bit 0 of address 0FH and its MSB in bit 3 of address 0CH.

Figure 10-2. Data Buffer Configuration

Because the data buffer is allocated in data memory, it can be used in any of the data memory manipulation

instructions.

0123456789

Data buffer

(DBF)

Column address

Data memory

System register (SYSREG)

BANK0

0DH

0CH

Address

Data

Data buffer

0FH

0EH

b11 b10 b9

b15 b14 b13 b12

Data memory

BANK0

Bit

Symbol

Data

DBF3

DBF2

DBF1

DBF0

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