UPD17P136ACT datasheet(67/292 Pages) NEC

67 / 292 page

CHAPTER 7 SYSTEM REGISTER (SYSREG)

Figure 7-9. Modification of Data Memory Address by Index Register and Memory Pointer

Data memory address specified by m

Indirect transfer address specified by @r

IXE

MPE

BANK

(r)

MPL

(r)

BANK

IXH

IXM

Setting prohibited

Row address

Bank

Column address

Row address

Bank

Column address

Logical OR

MPH

BANK

IXH

IXM

Logical OR

IXL

BANK

BANK : Bank register

: Index register

IXE

: Index enable flag

IXH

: Bits 10 through 8 of index register

IXM : Bits 7 through 4 of index register

IXL

: Bits 3 through 0 of index register

: Data memory indicated by mR and mC

: Data memory row address

: Data memory column address

: Memory pointer

MPE : Memory pointer enable flag

MPH : High-order 3 bits of memory pointer

MPL : Low-order 4 bits of memory pointer

: General register column address

: General register pointer

(

×)

: Contents addressed by

×: Direct address such as r

Table 7-2. Instructions Subject to Address Modification

Arithmetic

ADD

r, m

operation

ADDC

SUB

m, #n4

SUBC

Logical

AND

operation

r, m

XOR

m, #n4

Judgment

SKT

m, #n

SKF

Compare

SKE

SKGE

m, #n4

SKLT

SKNE

Transfer

r, m

m, r

MOV

m, #n4

@r, m

m, @r

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