FS32K112BHTXMLFTR datasheet(12/100 Pages) NXP

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6. This is the Electronic Control Unit (ECU) supply ramp rate and not directly the MCU ramp rate. Limit applies to both

maximum absolute maximum ramp rate and typical operating conditions.

7. This is the MCU supply ramp rate and the ramp rate assumes that the S32K1xx HW design guidelines in AN5426 are

followed. Limit applies to both maximum absolute maximum ramp rate and typical operating conditions.

8. TJ (Junction temperature)=TBD. Assumes TA=150 °C for RUN mode

• Assumes maximum

θJA for 2s2p board. See Thermal characteristics

9. 60 seconds lifetime; device in reset (no outputs enabled/toggling)

4.2 Voltage and current operating requirements

NOTE

Device functionality is guaranteed up to the LVR assert level,

however electrical performance of 12-bit ADC, CMP with 8-bit

DAC, IO electrical characteristics, and communication modules

electrical characteristics would be degraded when voltage drops

below 2.7 V

Table 3. Voltage and current operating requirements for S32K1xx series 1

Symbol

Description

Min.

Max.

Unit

Notes

VDD2

Supply voltage

2.73

5.5

VDD_OFF

Voltage allowed to be developed on VDD

pin when it is not powered from any

external power supply source.

0.1

VDDA

Analog supply voltage

2.7

5.5

VDD – VDDA

VDD-to-VDDA differential voltage

– 0.1

0.1

VREFH

ADC reference voltage high

2.7

VDDA + 0.1

VREFL

ADC reference voltage low

-0.1

0.1

VODPU

Open drain pullup voltage level

VDD

IINJPAD_DC_OP7

Continuous DC input current (positive /

negative) that can be injected into an I/O

-3

IINJSUM_DC_OP

Continuous total DC input current that can

be injected across all I/O pins such that

there's no degradation in accuracy of

analog modules: ADC and ACMP (See

section Analog Modules)

—

1. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise

stated.

2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the

ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details.

3. S32K148 will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged S32K148 is guaranteed to

operate from 2.97 V. All other S32K family devices operate from 2.7 V in all modes.

4. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC

only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for

reference supply design for SAR ADC.

5. VREFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V

6. Open drain outputs must be pulled to VDD.

7. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible.

General

S32K1xx Data Sheet, Rev. 12, 02/2020

NXP Semiconductors

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