FS32K112BHTXMLFTR datasheet(91/100 Pages) NXP

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Pinouts

9.1 Package pinouts and signal descriptions

For package pinouts and signal descriptions, refer to the Reference Manual.

10 Revision History

The following table provides a revision history for this document.

Table 57. Revision History

Rev. No.

Date

Substantial Changes

12 Aug 2016

Initial release

03 March 2017

• Updated descpition of QSPI and Clock interfaces in Key Features section

• Updated figure: High-level architecture diagram for the S32K1xx family

• Updated figure: S32K1xx product series comparison

• Added note in section Selecting orderable part number

• Updated figure: Ordering information

• In table: Absolute maximum ratings :

• Added footnote to IINJPAD_DC

• Updated min and max value of IINJPAD_DC

• Updated description, max and min values for IINJSUM

• Updated VIN_TRANSIENT

• In table: Voltage and current operating requirements :

• Renamed VSUP_OFF

• Updated max value of VDD_OFF

• Removed VINA and VIN

• Added VREFH and VREFL

• Updated footnote "Typical conditions assumes VDD = VDDA = VREFH = 5

V ...

• Removed INJSUM_AF

• Updated footnotes in table Table 7

• Updated section Power mode transition operating behaviors

• In table: Power consumption

• Added footnote "With PMC_REGSC[CLKBIASDIS] ... "

• Updated conditions for VLPR

• Removed Idd/MHz for S32K144

• Updated numbers for S32K142 and S32K148

• Removed use case footnotes

• In section Modes configuration :

• Replaced table "Modes configuration" with spreadsheet attachment:

'S32K1xx_Power_Modes _Master_configuration_sheet'

• In table: DC electrical specifications at 3.3 V Range :

• Added footnotes to Vih Input Buffer High Voltage and Vih Input Buffer

Low Voltage

• Added footnote to High drive port pins

• In table: DC electrical specifications at 5.0 V Range :

Table continues on the next page...

Pinouts

S32K1xx Data Sheet, Rev. 12, 02/2020

NXP Semiconductors

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