FS32K112BHTXMLFTR datasheet(39/100 Pages) NXP

tên linh kiện	FS32K112BHTXMLFTR

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Table 28. External System Oscillator frequency specifications

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

S32K14x/

S32K14xW

S32K11x

S32K14x/

S32K14xW

S32K11x

S32K14x/

S32K14xW

S32K11x

fosc_hi

Oscillator crystal or resonator

frequency

—

40 1, 2

MHz

fec_extal

Input clock frequency (external clock

mode)

—

MHz

tdc_extal

Input clock duty cycle (external clock

mode)

tcst

Crystal Start-up Time

8 MHz low-gain mode (HGO=0)

—

1.5

—

8 MHz high-gain mode (HGO=1)

—

2.5

—

40 MHz low-gain mode (HGO=0)

—

40 MHz high-gain mode (HGO=1)

—

For an ideal clock of 40 MHz, if permitted by application requirements, an error of +/- 5% is supported with 50% duty cycle.

In S32K14xW, when sourcing ADC clock from oscillator, a better duty cycle is expected.

Frequencies below 40 MHz can be used for degraded duty cycle upto 40-60%. In S32K14xW, when sourcing ADC clock from oscillator, a better duty cycle is

expected. To cater for the duty cycle requirement or to limit the ADC clock to ≤ fADCK, the divider ADCn.ADC_CFG1[ADICLK] for the specific ADC instance can be

used.

Proper PC board layout procedures must be followed to achieve specifications.

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