PFS172 datasheet(60/92 Pages) PADAUK

60 / 92 page

PFS172

8bit MTP MCU with 8-bit ADC

Page 60 of 92

PDK-DS-PFS172-EN_V000-May 8, 2020

6. IO Registers

6.1. ACC Status Flag Register (flag), IO address = 0x00

Bit

Reset

R/W

Description

7 - 4

Reserved. Please do not use.

R/W

OV (Overflow Flag). This bit is set to be 1 whenever the sign operation is overflow.

R/W

AC (Auxiliary Carry Flag). There are two conditions to set this bit, the first one is carry out

of low nibble in addition operation and the other one is borrow from the high nibble into low

nibble in subtraction operation.

R/W

C (Carry Flag). There are two conditions to set this bit, the first one is carry out in addition

operation, and the other one is borrow in subtraction operation. Carry is also affected by

shift with carry instruction.

R/W

Z (Zero Flag). This bit will be set when the result of arithmetic or logic operation is zero;

Otherwise, it is cleared.

6.2. Stack Pointer Register (sp), IO address = 0x02

Bit

Reset

R/W

Description

7 - 0

R/W

Stack Pointer Register. Read out the current stack pointer, or write to change the stack

pointer.

6.3. Clock Mode Register (clkmd), IO address = 0x03

Bit

Reset

R/W

Description

7 - 5

111

R/W

System clock (CLK) selection:

Type 0, clkmd[3]=0

Type 1, clkmd[3]=1

000: IHRC÷4

001: IHRC÷2

010: reserved

011: EOSC÷4

100: EOSC÷2

101: EOSC

110: ILRC÷4

111: ILRC (default)

000: IHRC÷16

001: IHRC÷8

010: ILRC÷16 (ICE does NOT Support.)

011: IHRC÷32

100: IHRC÷64

101: EOSC÷8

11x: reserved.

R/W

Internal High RC Enable. 0 / 1: disable / enable

R/W

Clock Type Select. This bit is used to select the clock type in bit [7:5].

0 / 1: Type 0 / Type 1.

R/W

Internal Low RC Enable. 0 / 1: disable / enable

If ILRC is disabled, watchdog timer is also disabled.

R/W

Watch Dog Enable. 0 / 1: disable / enable

R/W

Pin PA5/PRSTB function. 0 / 1: PA5 / PRSTB.

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