PFS172 datasheet(4/92 Pages) PADAUK

4 / 92 page

PFS172

8bit MTP MCU with 8-bit ADC

Page 4 of 92

PDK-DS-PFS172-EN_V000-May 8, 2020

5.4.5.

System Clock and LVR level......................................................................................33

5.4.6.

System Clock Switching ............................................................................................34

5.5.

Comparator ...........................................................................................................................35

5.5.1

Internal reference voltage (Vinternal R)...........................................................................36

5.5.2

Using the comparator ................................................................................................38

5.5.3

Using the comparator and bandgap 1.20V.................................................................39

5.6

16-bit Timer (Timer16) ..........................................................................................................40

5.7

8-bit Timer (Timer2/Timer3) with PWM generation ................................................................42

5.7.1

Using the Timer2 to generate periodical waveform ....................................................43

5.7.2

Using the Timer2 to generate 8-bit PWM waveform...................................................45

5.7.3

Using the Timer2 to generate 6-bit PWM waveform...................................................46

5.7.4

Complementary PWM with Dead Zones ....................................................................47

5.8

WatchDog Timer ...................................................................................................................50

5.9

Interrupt ................................................................................................................................50

5.10

Power-Save and Power-Down ..............................................................................................53

5.10.1 Power-Save mode (“stopexe”) ...................................................................................53

5.10.2 Power-Down mode (“stopsys”) ..................................................................................54

5.10.3 Wake-up ....................................................................................................................55

5.11

IO Pins ..................................................................................................................................56

5.12

Reset and LVR......................................................................................................................57

5.12.1 Reset.........................................................................................................................57

5.12.2 LVR reset ..................................................................................................................57

5.13

Analog-to-Digital Conversion (ADC) module .........................................................................57

5.13.1 The input requirement for AD conversion...................................................................58

5.13.2 ADC clock selection...................................................................................................59

5.13.3 Configure the analog pins..........................................................................................59

5.13.4 Using the ADC...........................................................................................................59

6. IO Registers ........................................................................................................................ 60

6.1.

ACC Status Flag Register (flag), IO address = 0x00 .............................................................60

6.2.

Stack Pointer Register (sp), IO address = 0x02.....................................................................60

6.3.

Clock Mode Register (clkmd), IO address = 0x03 .................................................................60

6.4.

Interrupt Enable Register (inten), IO address = 0x04.............................................................61

6.5.

Interrupt Request Register (intrq), IO address = 0x05 ...........................................................61

6.6.

Timer16 mode Register (t16m), IO address = 0x06...............................................................62

6.7.

External Oscillator setting Register (eoscr), IO address = 0x0a.............................................62

6.8.

Interrupt Edge Select Register (integs), IO address = 0x0c ...................................................63

6.9.

Port A Digital Input Enable Register (padier), IO address = 0x0d ..........................................63

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