PFS154 datasheet(70/91 Pages) PADAUK

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PFS154

8bit MTP Type IO Controller

Page 70 of 91

PDK-DS-PFS154_CN_V105 –Jun. 9, 2020

6.41. PWMG2 Scalar Register (pwmg2s), IO address = 0x2d

Bit

Reset

R/W

Description

PWMG2 interrupt mode.

0: Generate interrupt when counter matches the duty value

1: Generate interrupt when counter is 0.

6 - 5

PWMG2 clock pre-scalar.

00 : ÷1

01 : ÷4

10 : ÷16

11 : ÷64

4 - 0

PWMG2 clock divider.

6.42. PWMG2 Counter Upper Bound High Register (pwmg2cubh), IO address = 0x30

Bit

Reset

R/W

Description

7 - 0

Bit[10:3] of PWMG2 counter upper bound.

6.43. PWMG2 Counter Upper Bound Low Register (pwmg2cubl), IO address = 0x31

Bit

Reset

R/W

Description

7 - 6

Bit[2:1] of PWMG2 counter upper bound.

5 - 0

Reserved

6.44. PWMG2 Duty Value High Register (pwmg2dth), IO address = 0x2e

Bit

Reset

R/W

Description

7 - 0

Duty values bit[10:3] of PWMG2.

6.45. PWMG2 Duty Value Low Register (pwmg2dtl), IO address = 0x2f

Bit

Reset

R/W

Description

7 - 5

Duty values bit[2:0] of PWMG2.

4 - 0

Reserved

Note: It’s necessary to write PWMG2 Duty_Value Low Register before writing PWMG2 Duty_Value High Register.

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