PFS154 datasheet(41/91 Pages) PADAUK

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PFS154

8bit MTP Type IO Controller

Page 41 of 91

PDK-DS-PFS154_CN_V105 –Jun. 9, 2020

5.9. IO Pins

Other than PA5, all the pins can be independently set into two states output or input by configuring the data

registers (pa/pb), control registers (pac/pbc) and pull-high registers (paph/pbph). All these pins have

Schmitt-trigger input buffer and output driver with CMOS level. When it is set to output low, the pull-up resistor

is turned off automatically. If user wants to read the pin state, please notice that it should be set to input mode

before reading the data port; if user reads the data port when it is set to output mode, the reading data comes

from data register, NOT from IO pad. As an example, Table 7 shows the configuration table of bit 0 of port A.

The hardware diagram of IO buffer is also shown as Fig. 7.

Table 7: PA0 Configuration Table

Fig. 7: Hardware diagram of IO buffer

Most IOs can be adjusted their Driving or Sinking current capability to Normal or Low by code option Drive.

Other than PA5, all the IO pins have the same structure; PA5 can be open-drain ONLY when setting to output

mode (without Q1). When PFS154 put in power-down or power-save mode, every pin can be used to wake-up

system by toggling its state. Therefore, those pins needed to wake-up system must be set to input mode and

set the corresponding bits of registers pxdier to high. The same reason, padier.0 should be set to high when

PA0 is used as external interrupt pin.

pa.0

pac.0 paph.0

Description

Input without pull-up resistor

Input with pull-up resistor

Output low without pull-up resistor

Output high without pull-up resistor

Output high with pull-up resistor

(weak P-MOS)

PAD

WR pull-high latch

WR data latch

WR control latch

RD pull-high latch

RD control latch

RD Port

pull-high

latch

Data

latch

Control

latch

Data Bus

Analog Module

padier .x

Wakeup module

Interrupt module

(weak P-MOS)

PAD

WR pull-high latch

WR data latch

WR control latch

RD pull-high latch

RD control latch

RD Port

pull-high

latch

Data

latch

Control

latch

Data Bus

Analog Module

Wakeup module

Interrupt module

(PA0 only)

(weak P-MOS)

PAD

WR pull-high latch

WR data latch

WR control latch

RD pull-high latch

RD control latch

RD Port

pull-high

latch

Data

latch

Control

latch

Data Bus

Analog Module

padier .x

Wakeup module

Interrupt module

(weak P-MOS)

PAD

WR pull-high latch

WR data latch

WR control latch

RD pull-high latch

RD control latch

RD Port

pull-high

latch

Data

latch

Control

latch

Data Bus

Analog Module

Wakeup module

Interrupt module

(PA0 only)

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