PFS154 datasheet(42/91 Pages) PADAUK

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PFS154

8bit MTP Type IO Controller

Page 42 of 91

PDK-DS-PFS154_CN_V105 –Jun. 9, 2020

5.10. Reset and LVR

5.10.1 Reset

There are many causes to reset the PFS154, once reset is asserted, all the registers in PFS154 will be set to

default values, system should be restarted once abnormal cases happen, or by jumping program counter to

address 0x0. The data memory is in uncertain state when reset comes from power-up and LVR; however, the

content will be kept when reset comes from PRST# pin or WDT timeout.

5.10.2 LVR reset

By code option LVR, there are 8 different levels of LVR for reset: 4.0V, 3.5V, 3.0V, 2.75V, 2.5V, 2.2V, 2.0V and

1.8V, usually, user selects LVR reset level to be in conjunction with operating frequency and supply voltage.

5.11. VDD/2 Bias Voltage Generator

This function can be enabled by misc.4 and code option LCD2. To use this function, user must select

PB0_A034 for LCD2 and set misc.4 to 1 in the program. Those pins which are defined to output VDD/2

voltage are PB0, PA0, PA4 and PA3 during input mode, being used as COM function for LCD application. If

user wants to output VDD, VDD/2, GND three levels voltage, the corresponding pins must be set to output-high

for VDD, enabling VDD/2 bias voltage with input mode for VDD/2, and output-low for GND correspondingly,

Fig.8 shows how to use this function.

Pin set to output high

Pin set to input

Pin set to output low

VDD

VDD/2

GND

Fig. 8: Using VDD/2 bias voltage generator

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