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DS00003038B-page 69
KSZ8893FQL
Register 66 (0x42): Center Side Command
7-5
Timer Delay
R/W
000 = Reserved (Do Not Use)
001 = 32 μs (default)
010 = 128 μs
011 = 256 μs
100 = 512 μs
101 = 1 ms
110 = 2 ms
111 = 4 ms
001
4
Com4
R/W
To send a maintenance frame, an external controller
writes to these command bits via the SMI, SPI, or I2C
interface.
0 0000 : No request
0 0001 : Send “Condition Inform Request” frame
0 0010 : Send “Loop Mode Start Request” frame
0 0100 : Send “Loop Mode Stop Request” frame
0 1000 : Send “Remote Command”. Here, the Main-
tenance frame will be made up of the “Condition
Inform Request/Reply” frame, but the My Model Info
bits MM24-MM47 will be mapped to Registers 4Ah-
4Ch, instead of Registers 55h-57h.
1 0000 : Send “Indicate Center/Terminal MC Condi-
tion” frame. Usually, “Indicate Center/Terminal MC
Condition” frame will be sent automatically. But this
OAM frame can be sent manually using this com-
mand.
Other values : N/A
Note: Except for the “Indicate Center/Terminal MC
Condition” frame, all maintenance frames here are
sent by the Center side MC only.
0
3
Com3
R/W
0
2
Com2
R/W
0
1
Com1
R/W
0
0
Com0
R/W
0
Register 67 (0x43): PHY-SW Initialize
7
P2 SPEED
R/W
1 = 100 Mbps
0 = 10 Mbps
This bit share the same physical register as Reg. 2Ch
bit 6.
P2SPD pin
value during
reset
6
P2 DUPLEX
R/W
1 = Full-duplex
0 = Half-duplex
This bit share the same physical register as Reg. 2Ch
bit 5.
P2DPX pin
value during
reset
5
P2 Auto Negotiation
R/W
1 = AN enable
0 = AN disable
This bit share the same physical register as Reg. 2Ch
bit 7.
P2ANEN pin
value during
reset
4
SW Reset
R/W
1 = Reset MC sub-layer, MACs of both PHY ports and
switch fabric to their default states. This bit is self-
cleared after a ‘1’ is written to it.
0 = Normal operation
0
3
Remote Command
Enable
R/W
1 = Enable “Remote Command” access at Center
side and Terminal side
0 = Disable “Remote Command” access at Center
side and Terminal side
0
TABLE 4-9:
TS-1000 MEDIA CONVERTER REGISTERS (CONTINUED)
Bit
Name
R/W
Description
Default



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