KSZ8893FQL datasheet(52/109 Pages) MICROCHIP

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 2019 Microchip Technology Inc.

DS00003038B-page 51

KSZ8893FQL

Start Switch

R/W

1 = Start the chip when external pins (PS1, PS0) =

(0,1) or (1,0) or (1,1).

Note: In (PS1, PS0) = (0, 0) mode, the chip will start

automatically after trying to read the external

EEPROM. If EEPROM does not exist, the chip will

use pin strapping and default values for all internal

registers. If EEPROM is present, the contents in the

EEPROM will be checked. The switch will check: (1)

this check is OK, the contents in the EEPROM will

override chip registers’ default values.

0 = Chip will not start when external pins (PS1, PS0) =

(0,1) or (1,0) or (1,1).

New Back-Off

Enable

R/W

New back-off algorithm designed for UNH

1 = Enable

0 = Disable

6-4

Reserved

Reserved, Do not change the default value

100

Pass Flow Control

Packet

R/W

1 = Switch will pass 802.1x flow control packets

0 = Switch will drop 802.1x flow control packets

Reserved

R/W

Reserved

Do not change the default value.

Reserved

R/W

Reserved

Do not change the default value.

Link Change Age

R/W

Link change from “link” to “no link” will cause fast

aging (<800 μs) to age address table faster. After an

age cycle is complete, the age logic will return to nor-

mal aging (about 200 sec).

1 = Enable

0 = Disable

Note: If any port is unplugged, all addresses will be

automatically aged out.

Pass All Frames

R/W

1 = Switch all packets including bad ones. Used solely

for debugging purposes. Works in conjunction with

sniffer mode only.

Reserved

R/W

Reserved

Do not change the default value.

IEEE 802.3x

Transmit Direction

Flow Control Enable

R/W

1 = Will enable transmit direction flow control feature.

0 = Will not enable transmit direction flow control fea-

ture. Switch will not generate any flow control

(PAUSE) frame.

IEEE 802.3x

Receive Direction

Flow Control Enable

R/W

1 = Will enable receive direction flow control feature.

0 = Will not enable receive direction flow control fea-

ture. Switch will not react to any flow control (PAUSE)

frame it receives.

Frame Length Field

Check

R/W

1 = Will check frame length field in the IEEE packets.

If the actual length does not match, the packet will be

dropped (for Length/Type field < 1500).

0 = Will not check

TABLE 4-7:

GLOBAL REGISTERS (0-15) (CONTINUED)

Bit

Name

R/W

Description

Default

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