KSZ8893FQL datasheet(29/109 Pages) MICROCHIP

29 / 109 page

FIGURE 3-7:

DESTINATION ADDRESS RESOLUTION FLOW CHART, STAGE 2

Spanning Tree

Process

PTF1

IGMP Process

Port Mirror

Process

Port VLAN

Membership

Check

PTF2

- Check receiving port's receive enable bit

- Check destination port's transmit enable bit

- Check whether packets are special (BPDU

or specified)

- RX Mirror

- TX Mirror

- RX or TX Mirror

- RX and TX Mirror

- Applied to MAC #1 and MAC #2

- MAC #3 is reserved for

microprocessor

- IGMP will be forwarded to port 3

KSZ8893FQL

DS00003038A-page 28

 2019 Microchip Technology Inc.

The KSZ8893FQL will not forward the following packets:

Error packets: These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal

size packet errors.

IEEE802.3x PAUSE frames: KSZ8893FQL intercepts these packets and performs full-duplex flow control accord-

ingly.

"Local" packets: Based on destination address (DA) lookup. If the destination port from the lookup table matches

the port from which the packet originated, the packet is defined as local.

3.3.6

SWITCHING ENGINE

The KSZ8893FQL features a high-performance switching engine to move data to and from the MAC’s packet buffers.

It operates in store and forward mode, while the efficient switching mechanism reduces overall latency.

The switching engine has a 32 kB internal frame buffer. This buffer pool is shared between all three ports. There are a

total of 256 buffers available. Each buffer is sized at 128 bytes.

3.3.7

MAC OPERATION

The KSZ8893FQL strictly abides by IEEE 802.3 standards to maximize compatibility.

3.3.7.1

Inter Packet Gap (IPG)

If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If the

current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN.

3.3.7.2

Back-Off Algorithm

The KSZ8893FQL implements the IEEE 802.3 standard for the binary exponential back-off algorithm, and optional

"aggressive mode" back-off. After 16 collisions, the packet is optionally dropped depending on the switch configuration

for register 4 (0x04) bit [3].

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