MAX15014 datasheet(20/25 Pages) MAXIM

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fC occurs between fZ2 and fP2. In this region, the

compensatorgain (GEA) at fC is due primarily to C6 and

R5. Therefore, GEA(fC) = 2π x fC x C6 x R5 and the

modulator gain at fC is:

MOD_DC

MOD C

OUT

(f )

f )

L C

π×

× ×

Since GEA(fC) x GMOD(fC) = 1, R5 is calculated by:

OUT

MOD_DC

C6 G

× ×

× π

The frequency of fZ1 is set to 0.5 x fLC and now we can

calculate C7 by:

0.5 2

R5 f

× π×

fP2 is set at 1/2 the switching frequency (fSW). R6 is then

calculated by:

C6 (0.5 f

)

π×

Note that if the crossover frequency has been chosen as

1/10 of the switching frequency, then fP2 = 5xfC.

The purpose of fP3 is to further attenuate the residual

switching ripple at the COMP pin.

If the ESR zero (fZESR) occurs in a region between fC and

fSW/2, then fP3 can be used to cancel it. This way, the

Bode plot of the loop-gain plot does not flatten out soon

after the 0dB crossover, and maintains its -20dB/decade

slope up to 1/2 of the switching frequency.

If the ESR zero well exceeds fSW/2 (or even fSW), fP3

should in any case be set high enough not to erode the

phase margin at the crossover frequency. For example, it

can be set between 5 x fC and 10 x fC.

The value for C8 is calculated from:

C7 R5 f

π×

−

Compensation when fC > fZESR

For larger ESR capacitors such as tantalum and

aluminum electrolytic, fZESR can occur before fC. If fZESR

< fC, then fC occurs between fP2 and fP3. fZ1 and fZ2

remain the same as before; however, fP2 is now set equal

to fZESR. The output capacitor’s ESR zero frequency is

higher than fLC but lower than the closed-loop crossover

frequency. The equations that define the error amplifier’s

poles and zeros (fZ1, fZ2, fP2, and fP3) are the same as

before; however, fP2 is now lower than the closed-loop

crossover frequency. Figure 4 shows the error-amplifier

feedback as well as its gain response for circuits that

use higher-ESR output capacitors (tantalum or aluminum

electrolytic).

Again, starting from R3, calculate C6 for zero fZ2:

π×

and then place fP2 to cancel the ESR zero. R6 is

calculated as:

OUT

ESR

If the value obtained here for R6 is not considerably

smaller than R3, recalculate C6 using (R3 + R6) in place

of R3. Then use the new value of C6 to obtain a better

approximation for R6. The process can be further iterated,

and convergence is ensured as long as fLC < fZESR.

Figure 4. Error Amplifier Compensation Circuit (Closed-

Loop and Error-Amplifier Gain Plot) for Higher ESR Output

Capacitors

GAIN

(dB)

VOUT

REF

COMP

FREQUENCY

CLOSED-LOOP

GAIN

fZ1 fZ2

fP2

fP3

MAX15014–MAX15017

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

www.maximintegrated.com

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