MAX15014 datasheet(18/25 Pages) MAXIM

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ESR

OUT_MAX

ESR

−

∆

∆×

where CIN is the sum of CDRAIN and additional decoupling

capacitance at the buck converter input,

OUT

) V

and

−

−×

∆=

××

IOUT_MAX is the maximum output current, D is the duty

cycle, and fSW is the switching frequency.

The MAX15014–MAX15017 include UVLO hysteresis

and soft-start to avoid chattering during turn-on. However,

use additional bulk capacitance if the input source

impedance is high. Use enough input capacitance

at lower input voltages to avoid possible undershoot

below the undervoltage-lockout threshold during transient

Output Capacitor Selection

The allowable output-voltage ripple and the maximum

deviation of the output voltage during load steps deter-

mine the output capacitance (COUT) and its equivalent

series resistance (ESR). The output ripple is mainly

composed of ΔVQ (caused by the capacitor discharge)

and ΔVESR (caused by the voltage drop across the ESR

of the output capacitor). The equations for calculating the

peak-to-peak output-voltage ripple are:

OUT

ESR

P P

ESR

−

∆

∆=

××

∆

×∆

Normally, a good approximation of the output-voltage

ripple is ΔVRIPPLE = ΔVESR + ΔVQ. If using ceramic

capacitors, assume the contribution to the output-voltage

ripple from ESR and the capacitor discharge to be equal

to 20% and 80%, respectively. ΔIP-P is the peak-to-

peak inductor current (see the Input Capacitor Selection

section) and fSW is the converter’s switching frequency.

The allowable deviation of the output voltage during fast-

load transients also determines the output capacitance,

its ESR, and its equivalent series inductance (ESL).

The output capacitor supplies the load current during

a load step until the controller responds with a greater

duty cycle. The response time (tRESPONSE) depends

on the closed-loop bandwidth of the converter (see

the Compensation Design section). The resistive drop

across the output capacitor’s ESR, the drop across the

capacitor’s ESL (ΔVESL), and the capacitor discharge

causes a voltage droop during the load step.

Use a combination of low-ESR tantalum/aluminum

electrolytic and ceramic capacitors for better

transient load and voltage-ripple performance. Non-leaded

capacitors and capacitors in parallel help reduce the ESL.

Keep the maximum output-voltage deviation below the

tolerable limits of the electronics being powered. Use the

following equations to calculate the required ESR, ESL,

and capacitance value during a load step:

ESR

STEP

RESPONSE

OUT

ESL

STEP

RESPONSE

ESR

ESL

≅

∆

∆×

where ISTEP is the load step, tSTEP is the rise time of

the load step, tRESPONSE is the response time of the

controller, and fC is the closed-loop crossover frequency.

Compensation Design

The MAX15014–MAX15017 use a voltage-mode-control

scheme that regulates the output voltage by comparing

the error-amplifier output (COMP) with an internal ramp

to produce the required duty cycle. The output lowpass

LC filter creates a double pole at the resonant frequency,

which has a gain drop of -40dB/decade. The error ampli-

fier must compensate for this gain drop and phase shift to

achieve a stable closed-loop system.

The basic regulator loop consists of a power modulator,

an output feedback-divider, and a voltage error amplifier.

The power modulator has a DC gain set by VIN/VRAMP,

with a double pole and a single zero set by the output

inductance (L), the output capacitance (COUT), and its

ESR. The power modulator incorporates a voltage feed-

forward feature, which automatically adjusts for variations

in the input voltage, resulting in a DC gain of 10.

MAX15014–MAX15017

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

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