MAX15014 datasheet(19/25 Pages) MAXIM

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The following equations define the power modulator:

MOD_DC

RAMP

OUT

ZESR

OUT

ESR

× π×

The switching frequency is internally set at 500kHz

for MAX15015/MAX15017 and can vary from 400kHz

to 600kHz when driven with an external SYNC signal.

The switching frequency is internally set at 135kHz for

MAX15014/MAX15016 and can vary from 100kHz to

200kHz when driven with an external SYNC signal. The

crossover frequency (fC), which is the frequency when the

closed-loop gain is equal to unity, should be set to around

1/10 of the switching frequency or below.

The crossover frequency occurs above the LC double-pole

frequency, and the error amplifier must provide a gain and

phase bump to compensate for the rapid gain and phase

loss from the LC double pole, which exhibits little damping.

This is accomplished by utilizing a Type 3 compensator

that introduces two zeroes and three poles into the control

loop. The error amplifier has a low-frequency pole (fP1)

near the origin so that tight voltage regulation at DC can

be achieved.

The two zeroes are at:

R5 C7

π×

and

(R3 R6) C6

π ×

and the higher frequency poles are at:

R6 C6

π×

and

C7 C8

π×

The compensation design primarily depends on the type

of output capacitor. Ceramic capacitors exhibit very low

ESR, and are well suited for high-switching-frequency

applications, but are limited in capacitance value and

tend to be more expensive. Aluminum electrolytic capaci-

tors have much larger ESR but can reach much larger

capacitance values.

Compensation when fC < fZESR

This is usually the case when a ceramic capacitor is

selected. In this case, fZESR occurs after fC. Figure 3

shows the error amplifier feedback as well as its gain

response.

fZ1 is set to 0.5 to 0.8 x fLC and fZ2 is set to fLC to

compensate for the gain and phase loss due to the double

pole. To achieve a 0dB crossover with -20dB/decade

slope, poles fP2 and fP3 are set above the crossover

frequency (fC).

The values for R3 and R4 are already determined in the

Setting the Output Voltage section. The value of R3 is

also used in the following calculations.

Since fZ2 < fC < fP2, then R3 >> R6, and R3 + R6 can be

approximated as R3.

Now we can calculate C6 for zero fZ2:

π×

Figure 3. Error Amplifier Compensation Circuit (Closed-Loop

and Error-Amplifier Gain Plot) for Ceramic Capacitors

GAIN

(dB)

VOUT

REF

COMP

FREQUENCY

CLOSED-LOOP

GAIN

fZ1 fZ2

fP2 fP3

MAX15014–MAX15017

1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

www.maximintegrated.com

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