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FS98O02B-PCE bảng dữ liệu(PDF) 16 Page - Fortune Semiconductor Corp. |
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FS98O02B-PCE bảng dữ liệu(HTML) 16 Page - Fortune Semiconductor Corp. |
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16 / 50 page  FS98O02 Rev.1.5 16/50 conditional network control register, LCD driver. The address 80h~FFh areas are general data memory. Table 11-1: Data Memory Organization Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State WDT Reset State Details on page: 00h IND0 Use contents of FSR0 to address data memory uuuu uuuu uuuu uuuu 16 02h FSR0 Indirect data memory, address point 0 uuuu uuuu uuuu uuuu 16 04h STATUS PD TO DC C Z ---0 0uuu ---u 1uuu 16 05h WORK WORK register uuuu uuuu uuuu uuuu 16 06h INTF TMIF ADIF E0IF ---0 --00 ---0 –00 25, 27, 28 07h INTE GIE TMIE ADIE E0IE 0--0 --00 0--0 –00 25, 27, 28 08h~7Fh Peripheral special registers 18 80h~FFh General data memory (128-byte SRAM) uuuu uuuu uuuu uuuu Note 1: “u” means unknown or unchanged. “-“ means unimplemented, read as “0”. Note 2: The “Reset State” indicates the registers state after external reset and low voltage reset. Note 3: The “WDT Reset State” indicates the registers state after watchdog time out reset. 11.3 System Special Registers System special registers are used by the CPU to control the operation of the device. Some registers are used for data memory access, some for logic judgment, and some for arithmetic, etc. Table 11-2: System Special Registers Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset State WDT Reset State Details on page: 00h IND0 Use contents of FSR0 to address data memory uuuu uuuu uuuu uuuu 16 02h FSR0 Indirect data memory, address point 0 uuuu uuuu uuuu uuuu 16 04h STATUS PD TO DC C Z ---0 0uuu ---u 1uuu 16 05h WORK WORK register uuuu uuuu uuuu uuuu 16 06h INTF TMIF ADIF E0IF ---0 --00 ---0 --00 25, 27, 28 07h INTE GIE TMIE ADIE E0IE 0--0 --00 0--0 --00 25, 27, 28 Note 1: “u” means unknown or unchanged. “-“ means unimplemented, read as “0”. Note 2: The “Reset State” indicates the registers state after external reset and low voltage reset. Note 3: The “WDT Reset State” indicates the registers state after watchdog time out reset. IND0 : Address 00h The IND0 registers at data memory address are not physical registers. Any instruction using the IND0 register actually access the data pointed by the FSR0 register. A simple program to clear data memory 80h-0BFh using indirect addressing is shown as Example 11-1. MOVLW 080h MOVWF FSR0 NEXT: CLRF IND0 ; Clear the content of memory address pointed by FSR0 INCFSZ FSR0, 1 ; FSR0 = FSR0 + 1, and judge if FSR0 = 0 GOTO NEXT Example 11-1: Using Indirect Addressing |
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