FS98O02B-PCE datasheet(39/50 Pages) FORTUNE

39 / 50 page

FS98O02

Rev.1.5

39/50

(about 0 ~ 0.3V), the CPU will go into external reset status. The external R/C circuit for reset is shown as

following. When VDD changes from “low” to “high”, the CPU external reset status will be released, and the CPU

will be in normal operating condition.

The signal from the “VPP/RST/TST” pin to CPU should remain in logic “low” state for more than 2μs to

reset the CPU. If the signal from the “VPP/RST/TST” pin to CPU is in “low” state less than 2μs, the CPU will not

be reset. Figure 19-2 shows the minimum reset period to reset the CPU.

Figure 19-1: the Reset Circuit and the Reset Timing

Figure 19-2: the Minimum Reset Period to Reset the CPU

19.2 Low Voltage Reset

To avoiding the CPU in an abnormal power status that makes the CPU unable to reset and causes the

CPU operating abnormally, there’s a low voltage reset circuit embedded in FS98O02. When the voltage of VDD

is less than LVR threshold low voltage, the CPU enters reset state; and when the voltage of VDD comes back

above the LVR threshold high voltage, the CPU will be in normal operating condition.

19.3 Watchdog Time Out Reset

The watchdog timer in FS98O02 is usually used to monitor if the CPU is in normal operation. If the CPU is

not in normal operation, we may use the watchdog timer to raise a watchdog time our reset and make the CPU

to be back in normal operation. The watchdog timer may be used to some period wakeup-and-measuring

applications to save the power for some long time monitoring portable applications.

Table 19-2: Watchdog Time Out Reset Related Registers

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset State

WDT Reset State

04h

STATUS

---0 0uuu

---u 1uuu

0Eh

TMCON

WDTEN

WTS [1:0]

1000 0000

1u00 0000

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