FS98O02B-PCE datasheet(30/50 Pages) FORTUNE

30 / 50 page

FS98O02

Rev.1.5

30/50

010

ADCF/500 (~80Hz for 1MHz MCK or ~320Hz for 4MHz MCK)

011

ADCF/1000 (~40Hz for 1MHz MCK or ~160Hz for 4MHz MCK)

100

ADCF/2000 (~20Hz for 1MHz MCK or ~80Hz for 4MHz MCK)

101

ADCF/4000 (~10Hz for 1MHz MCK or ~40Hz for 4MHz MCK)

110

ADCF/8000 (~5Hz for 1MHz MCK or ~20Hz for 4MHz MCK)

16.3.2

ADC Input Offset

The ADC input offset voltage, Vio drifts with temperature and common mode voltage at the inputs. When

AZ = 0, the ΔΣ modulator’s differential inputs are (VIH, VIL); when AZ = 1, the ΔΣ modulator’s differential inputs

are (VIL, VIL). We can set AZ = 1 to measure the ADC’s offset.

When the drifting is slow, we may set AZ = 1, and get Doff = 15625 * G * (Vio) / (VRH – VRL + Vro). When

measuring input signal, Doff should be deducted.

16.3.3

ADC Gain

The ADC digital output code deducted by Doff is the ADC Gain. The ADC gain does not change as VDD

changes. The suggested values for common mode voltages at ADC input and reference voltage are 1V~2V

respect to VSS. ADG [1:0] can set ADC’s input gain: 00 for 2/3, 01 for 1, 10 for 2, and 11 for 7/3.

16.3.4

ADC Resolution

The ADC resolution is mainly decided by ADM [2:0] (ADC output rate) and reference voltage, and the test

results in FSC are as below for users’ reference. When we set (VRH, VRL) = 0.4V, (VIH, VIL) = 0.2V, VRL = VIL

= AGND, G = 1, and record ADO [23:8], we get the result in Table 16-3

. When we set (VRH, VRL) = VR, (VIH, VIL) = 1/2 * VR, VRL = VIL = AGND, G = 1, ADM [2:0] = 101, and

record ADO [15:0], we get the result in Table 16-4.

Table 16-3

ADM [2:0]

000

001

010

011

100

101

110

Rolling counts

Table 16-4

VR (V)

0.05

0.1

0.2

0.3

0.4

0.6

0.8

1.0

Rolling counts

16.4 ADC Input Multiplexer and Low Pass Filter

There are several analog input multiplexers and a low pass filter in FS98O02. We may use the analog

input multiplexers and the low pass filter properly to measure the input signals well.

Table 16-5: ADC Input Multiplexer and Low Pass Filter Related Registers

Address

Name

Bit 7

Bit 6

Bit 5 Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset State

WDT Reset State

2Ah

NETB

SINL [1:0]

SINH [1:0] SFT [2]

SFT [0] ---0 00-0

---0 00-0

2Ch

NETD

SVRH [0] SVRL [1:0]

SLVD SVR

u000 uu00

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