Z86C34 datasheet(45/70 Pages) ZILOG

45 / 70 page

Z86C34/C35/C36/C44/C45/C46

ZiLOG

CMOS Z8® MCUs with ASCI UART

DS007601-Z8X0499

P R E L I M I N A R Y

a 0 to the EFR bit in CNTLA is the only way to clear these

latches. In other words, when an error bit reaches the top

of the FIFO, it sets an error latch. If the FIFO contains more

data and the software reads the next byte out of the FIFO,

the error latch remains set until the software writes a 0 to

the EFR bit. The error bits are cumulative, so if additional

errors are in the FIFO they set any unset error latches as they

reach the top.

Baud Rate Generator.

The baud rate generator features

two modes. The first provides a dual set of fixed clock di-

vide ratios as defined in CNTLB. In the second mode, the

BRG

is configured as a sixteen-bit down counter that divides

the processor clock by the value in a software accessible,

sixteen-bit, time-constant register. As a result, virtually any

frequency can be created by appropriately selecting the

main processor clock frequency. The BRG can also be dis-

abled in favor of the SCLK.

The Receiver and Transmitter subsequently divide the out-

put of the Baud rate Generator (or the signal from the CLK

pin) by 1, 16 or 64 under the control of the DR bit in the

CNTLB

trol Register (ASEXT).

RESET.

During RESET, the ASCI is forced to the following

conditions:

• FIFO Empty

• All Error Bits Cleared (including those in the FIFO)

• Receive Enable Cleared (CNTLA BIT 6 = 0)

• Transmit Enable Cleared (CNTLA BIT 5 = 0)

Figure 31. ASCI Interface Diagram

Internal Address/Data Bus

ASCI Transmit Data Register

ASCI Status FIFO/Register

TDR (Bank:Ah,Addr :01h)

ASCI Transmit Shift Register

TSR

ASCI Receive Data FIFO

RDR (Bank:Ah,Addr:02h)

ASCI Receive Shift Register

RSR

ASCI Control Register A

CNTLA (Bank:Ah,Addr:03h)

ASCI Control Register B

CNTLB (Bank:Ah,Addr:04h)

STAT (Bank:Ah,Addr:08h)

ASCI Extension Control Reg.

ASEXT (Bank:Ah,Addr:05h)

ASCI Time Constant High

ASCI Time Constant Low

ASTCL (Bank:Ah,Add:06h)r

Baud Rate Generator

SCLK

(P37) TX

(P30) RX

ASCI

Control

IRQ3

Interrupt Request

Note: **Not Program

Accessible

ASTCH (Bank:Ah,Addr:07h)

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