Z86C34 datasheet(35/70 Pages) ZILOG

35 / 70 page

Z86C34/C35/C36/C44/C45/C46

ZiLOG

CMOS Z8® MCUs with ASCI UART

DS007601-Z8X0499

P R E L I M I N A R Y

When more than one interrupt is pending, priorities are re-

solved by a programmable priority encoder that is con-

trolled by the Interrupt Priority register. An interrupt ma-

chine cycle activates when an interrupt request is granted.

This action disables all subsequent interrupts, saves the Pro-

gram Counter and Status Flags, and then branches to the

program memory vector location reserved for that interrupt.

All Z8 interrupts are vectored through locations in the pro-

gram memory. This memory location and the next byte con-

tain the 16-bit address of the interrupt service routine for

that particular interrupt request. To accommodate polled in-

terrupt systems, interrupt inputs are masked and the Inter-

rupt Request register is polled to determine which of the in-

terrupt requests require service.

Figure 23. Interrupt Block Diagram

Table 11. Interrupt Types, Sources, and Vectors

Name

Source

Vector

Location

Comments

IRQ0

DAV0, IRQ0

0, 1

External (P32), Rise Fall Edge Triggered

IRQ1,

IRQ1

2, 3

External (P33), Fall Edge Triggered

IRQ2

DAV2, IRQ2, TIN

4, 5

External (P31), Rise Fall Edge Triggered

IRQ3

UART (ASCI)

6, 7

External (P30), Fall Edge Triggered

IRQ4

8, 9

Internal

IRQ5

10, 11

Internal

Interrupt

Edge

Select

IRQ (D6, D7)

IRQ1, 3, 4, 5

IRQ

IMR

IPR

PRIORITY

LOGIC

Global

Interrupt

Enable

Vector Select

Interrupt

Request

IRQ0 IRQ2

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