DSP56857 datasheet(467/662 Pages) FREESCALE

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TAP Block Diagram

JTAG Port, Rev. 4

Freescale Semiconductor

17-5

17.4 TAP Block Diagram

Figure 17-1. Test Access Port (TAP) Block Diagram

Table 17-1. JTAG Pin Descriptions

Pin Name

Pin Description

TDI

Test Data Input—This input pin provides a serial input data stream to the JTAG and the EOnCE

modules. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.

TDO

Test Data Output—This tri-state output pin provides a serial output data stream from the JTAG

and the EOnCE modules. It is driven in the Shift-IR and Shift-DR controller states of the JTAG

state machine and changes on the falling edge of TCK.

TCK

Test Clock Input—This input pin provides the clock to synchronize the test logic and shift serial

data to and from all TAP Controllers and the TLM. If the EOnCE module is not being accessed

using the Master TAP Controllers, the maximum TCK frequency is 1/4 the maximum frequency for

the 56800E core. When accessing the EOnCE module through the 56800E core TAP Controller,

the maximum frequency for TCK is 1/8 the maximum frequency for the 56800E core.

The TCK pin has an on-chip pull-down resistor.

TMS

Test Mode Select Input—This input pin is used to sequence the JTAG TAP Controller’s state

machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor.

TRST

Test Reset—This input provides a reset signal to the JTAG TAP Controller. The TRST pin has an

on-chip pull-up resistor.

Debug Event—This output signal debugs events detected on a trigger condition.

Boundary Scan Register

Instruction Decode

TDI

TDO

TAP

TMS

TCK

TRST

IDCode Register

Bypass Register

Instruction Register

Controller

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