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DSP56857 bảng dữ liệu(PDF) 415 Page - Freescale Semiconductor, Inc |
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DSP56857 bảng dữ liệu(HTML) 415 Page - Freescale Semiconductor, Inc |
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415 / 662 page ![]() Register Descriptions General Purpose Input/Output (GPIO), Rev. 4 Freescale Semiconductor 15-15 15.8.11 Port C Data Direction Register (GPIOC_DDR) Figure 15-20. Port C Direction Register (GPIOC_DDR) See Programmer’s Sheet on Appendix page B - 115 15.8.11.1 Reserved—Bits 15–6 These bits are reserved or not implemented. They are read as 0 and cannot be modified by writing. 15.8.11.2 Data Direction (DD)—Bits 5–0 These bits control the pins direction when in the GPIO mode. These bits have no effect on the output enables or pull-up enables in the Normal mode. • 0 = Pin is an input; pull-ups are dependent on value of PUE registers (default) • 1 = Pin is an output; pull-ups are disabled 15.8.12 Port D Data Direction Register (GPIOD_DDR) Figure 15-21. Port D Direction Register (GPIOD_DDR) See Programmer’s Sheet on Appendix page B - 116 15.8.12.1 Reserved—Bits 15–6 These bits are reserved or not implemented. They are read as 0 and cannot be modified by writing. 15.8.12.2 Data Direction (DD)—Bits 5–0 These bits control the pins direction when in the GPIO mode. These bits have no effect on the output enables or pull-up enables in the Normal mode. • 0 = Pin is an input; pull-ups are dependent on value of PUE registers (default) • 1 = Pin is an output; pull-ups are disabled Base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 DD Write Reset 00 000 00 0 0 0 0 0 0 0 0 0 Base + $1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 0 0 0 DD Write Reset 00 000 00 0 0 0 0 0 0 0 0 0 |
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