DSP56857 datasheet(381/662 Pages) FREESCALE

381 / 662 page

Quad Timer (TMR), Rev. 4

Freescale Semiconductor

13-15

13.9.2.7 Input Polarity Select (IPS)—Bit 9

When set, this bit inverts the input signal polarity.

13.9.2.8 External Input Signal (INPUT)—Bit 8

This bit reflects the current state of the external input pin selected via the secondary count source

after application of the IPS bit. This is a read-only bit.

13.9.2.9 Input Capture Mode (Capture Mode)—Bits 7–6

These bits specify the operation of the Capture Register as well as the operation of the input edge

flag.

•

00 = Capture function is disabled

•

01 = Load Capture Register on rising edge of input

•

10 = Load Capture Register on falling edge of input

•

11 = Load Capture Register on any edge of input

13.9.2.10 Master Mode (MSTR)—Bit 5

When set, this bit enables the Compare function’s output to be broadcasted to the other

counter/timers in the module. This signal then can be used to reinitialize the other counters and/or

force their OFLAG signal outputs.

13.9.2.11 Enable External OFLAG Force (EEOF)—Bit 4

When set, this bit enables the compare from another counter/timer within the same module to

force the state of this counters’ OFLAG Output signal.

13.9.2.12 Forced OFLAG Value (VAL)—Bit 3

This bit determines the value of the OFLAG Output signal when a software triggered FORCE

command occurs.

13.9.2.13 Force OFLAG Output (FORCE)—Bit 2

This write-only bit forces the current value of the VAL bit to be written to the OFLAG Output.

Always read this bit as 0. The VAL and FORCE bits can be written simultaneously in a single

write operation. Write to the FORCE bit only if the counter is disabled.

•

0 = No action

•

1 = Forces the current value of the VAL bit to be written to OFLAG Output

Note:

Setting this bit while the counter is enabled may yield unpredictable results.

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