56F8014 datasheet(20/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 3

Freescale Semiconductor

Preliminary

GPIOB2

(MISO)

(T25)

Input/

Output

Input/

Output

Input/

Output

Input, pulled

high

internally

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

SPI Master In/Slave Out — This serial data pin is an input to a

master device and an output from a slave device. The MISO line of a

slave device is placed in the high-impedance state if the slave device

is not selected. The slave device places data on the MISO line a

half-cycle before the clock edge the master device uses to latch the

data.

T2 — Timer, Channel 2

After reset, the default state is GPIOB2. The peripheral functionality

is controlled via the SIM. See Section 6.3.8.

5. This signal is also brought out on the GPIOA4 pin.

GPIOB3

(MOSI)

(T36)

Input/

Output

Input/

Output

Input/

Output

Input, pulled

high

internally

Port B GPIO — This GPIO pin can be individually programmed as

an input or output pin.

SPI Master Out/Slave In— This serial data pin is an output from a

master device and an input to a slave device. The master device

places data on the MOSI line a half-cycle before the clock edge the

slave device uses to latch the data.

T3 — Timer, Channel 3

After reset, the default state is GPIOB3. The peripheral functionality

is controlled via the SIM. See Section 6.3.8.

6. This signal is also brought out on the GPIOA5 pin.

GPIOA0

(PWM0)

Input/

Output

Input, pulled

high

internally

Port A GPIO — This GPIO pin can be individually programmed as

an input or output pin.

PWM0 — This is one of the six PWM output pins.

After reset, the default state is GPIOA0.

Return to Table 2-2

Table 2-3 56F8014 Signal and Package Information for the 32-Pin LQFP (Continued)

Signal

Name

LQFP

Pin No.

Type

State During

Reset

Signal Description

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