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56F8014 bảng dữ liệu(PDF) 61 Page - Freescale Semiconductor, Inc |
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56F8014 bảng dữ liệu(HTML) 61 Page - Freescale Semiconductor, Inc |
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61 / 124 page ![]() Resets 56F8014 Technical Data, Rev. 3 Freescale Semiconductor 61 Preliminary 5.7 Resets 5.7.1 General 5.7.2 Description of Reset Operation 5.7.2.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address on the VAB pins whenever RESET is asserted from the SIM. The reset vector will be presented until the second rising clock edge after RESET is released. The general timing is shown in Figure 5-19 . Figure 5-19 Reset Interface 5.7.3 ITCN After Reset After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled, except the core IRQs with fixed priorities: • Illegal Instruction • SW Interrupt 3 • HW Stack Overflow • Misaligned Long Word Access • SW Interrupt 2 • SW Interrupt 1 • SW Interrupt 0 • SW Interrupt LP These interrupts are enabled at their fixed priority levels. Table 5-4 Reset Summary Reset Priority Source Characteristics Core Reset RST Core reset from the SIM RES CLK VAB PAB RESET_VECTOR_ADR READ_ADR |
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