56F8014 datasheet(55/124 Pages) FREESCALE

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56F8014 Technical Data, Rev. 3

Freescale Semiconductor

Preliminary

5.6.5.4

ADC Zero Crossing or Limit Error Interrupt Priority Level

(ADC_ZC_LE IPL)— Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.6.5.5

ADCB Conversion Complete Interrupt Priority Level

(ADCB_CC IPL)—Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2.

They are disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 0

•

10 = IRQ is priority level 1

•

11 = IRQ is priority level 2

5.6.6

Vector Base Address Register (VBA)

Figure 5-8 Vector Base Address Register (VBA)

5.6.6.1

Reserved—Bits15—14

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.6.2

Vector Address Bus (VAB)—Bits 13—0

The value in this register is used as the upper 14 bits of the interrupt vector VAB[20:0]. The lower 7 bits

are determined based on the highest priority interrupt and are then appended onto VBA before presenting

the full VAB to the Core.

5.6.7

Fast Interrupt Match 0 Register (FIM0)

Figure 5-9 Fast Interrupt Match 0 Register (FIM0)

Base + $5

Read

VECTOR_BASE_ADDRESS

Write

RESET

0000

Base + $6

Read

FAST INTERRUPT 0

Write

RESET

00000000

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