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AMD8513 bảng dữ liệu(PDF) 19 Page - Infineon Technologies AG |
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AMD8513 bảng dữ liệu(HTML) 19 Page - Infineon Technologies AG |
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19 / 88 page ![]() Data Sheet 19 Rev. 1.21, 2005-12-05 ADM8513 Data Sheet USB Commands The returned total number of registers depends on the length field. 5.1.2 Set Register (Vendor Specific) Burst Write Ex. Write 44 to RegIndex = 05H, the transfer will be If wLength > 1, more than 1 register is accessed (burst write) and mask is not supported => DataStage for 8-byte OUT transfer appears Ex. Burst write 20 registers from RegIndex = 07H and data from 01D to 20D • Setup Stage • Data Stage Table 16 Data Stage Offset0(1B) Offset1(1B) Offset2(1B) {RegIndex} {RegIndex+1) {RegIndex+2) Table 17 Setup Stage bmReq bReq wValue(2B) wIndexLow(1B) wIndexHigh(1B) wLength L(1B) wLength H(1B) 40 F1 0 RegIndex[7:0] 00 Length Low Length High Table 18 Data Stage Offset0(1B) Offset1(1B) Offset2(1B) Offset3(1B) {RegIndex} {RegIndex+1} {RegIndex+2} {RegIndex+3} Table 19 Setup Stage bmReq bReq wValue L(1B) wValue H(1B) wIndexLow (1B) wIndexHigh (1B) wLength L(1B) wLength H(1B) 40 F1 44 00 05 00 01 00 Table 20 Setup Stage bmReq bReq wValue(2B) wIndexLow(1B) wIndexHigh(1B) wLength L(1B) wLength H(1B) 40 F1 0000 07 00 14 00 Table 21 1st OUT Transfer Offset0(1B) Offset1(1B) Offset2(1B) Offset3(1B) Offset4(1B) Offset5(1B) Offset6(1B) Offset7(1B) 01 02 03 04 05 06 07 08 Table 22 2nd OUT Transfer Offset0(1B) Offset1(1B) Offset2(1B) Offset3(1B) Offset4(1B) Offset5(1B) Offset6(1B) Offset7(1B) 09 0A 0B 0C 0D 0E 0F 10 |
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