AMD8513 datasheet(68/88 Pages) INFINEON

68 / 88 page

ADM8513

Data Sheet

Registers Description

Data Sheet

Rev. 1.21, 2005-12-05

2. Reset the registers to their default values. Note that this does not affect registers 20, 22, 30 or 31. These

registers are not reset by this bit to allow test configurations to be written and then not affected by resetting the

port.

Note: No reset is performed to analogue sections of the port. There is also no physical reset to any internal

clock synthesisers or the local clock recovery oscillator which will continue to run throughout the reset period.

However since the port is restarted and autoneg re-run the process of locking the frequency of the local

oscillator (slave) to the reference oscillator (master) will be repeated as it is at the start of any link initialization

process.

LoopbackLoop back of transmit data to receive via a path as closed to the wire as possible. When set inhibits

actual transmission on the wire.

Speed SelectionForces speed of Phy only when auto-negotiation is disabled. The default state of this bit will be

determined by a power-up configuration pin in this case. Otherwise it defaults to 1.

Auto-neg EnableDefaults to pin programmed value. When cleared allows forcing of speed and duplex settings.

When set (after being cleared) causes re-start of auto-neg process. Pin programming at power-up allows it to

come up disabled and for software to write the desired capability before allowing the first negotiation to commence.

Restart NegotiationOnly has effect when auto-negotiating. Restarts state machine.

Power DownHas no effect in this device. Test mode power down modes may be implemented in other specific

modules.

IsolatePuts RMII receive signals into high impedance state and ignores transmit signals.

Duplex ModeWhen bit12 is cleared (i.e. autoneg disabled), this bit forces full duplex (bit = 1) or half duplex (bit =

0).

Collision TestAlways 0 because collision signal is not implemented.

Status

STA

Offset

Reset Value

Status

7849H

Field

Bits

Type

Description

100T4

100 BASE T4

Not supported

100FD

100BASE-X Full Duplex

100FDN, PHY is not 100BASE-X full duplex capable

100FD, PHY is 100BASE-X full duplex capable

100HD

100BASE-X Half Duplex

100HDN, PHY is not 100BASE-X half duplex capable

100HD, PHY is 100BASE-X half duplex capable

10FD

10 Mbit/s Full Duplex

10FDN, PHY is not 10 Mbit/s Full duplex capable

10FD, PHY is 10 Mbit/s Full duplex capable

AMD8513 bảng dữ liệu(PDF) 68 Page - Infineon Technologies AG

AMD8513 bảng dữ liệu(HTML) 68 Page - Infineon Technologies AG

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

bảng dữ liệu tải về

Link URL