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AMD8513 bảng dữ liệu(PDF) 48 Page - Infineon Technologies AG |
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AMD8513 bảng dữ liệu(HTML) 48 Page - Infineon Technologies AG |
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48 / 88 page ![]() ADM8513 Data Sheet Registers Description Data Sheet 48 Rev. 1.21, 2005-12-05 TS1 Offset Reset Value Transmit Status 1 2BH 00H Field Bits Type Description TXUE 7 r TX Underrun Error Set by HW to indicate tx underrun error. Clear by SW read this register or after EP3 is accessed. EC 6 r Excessive Collision Set by HW to indicate excessive collision. Clear by SW read this register or after EP3 is accessed. LC 5 r Late Collision Error Set by HW to indicate late collision error. Clear this register by SW Read or after EP3 is accessed. NC 4 r No Carrier Set by HW to indicate no carrier. Clear this register by SW Read or after EP3 is accessed. CL 3 r Carrier Loss Set by HW to indicate carrier loss. Clear this register by SW Read or after EP3 is accessed. JTO 2 r Jabber Time Out Set by HW to indicate jabber time out. Clear this register by SW Read or after EP3 is accessed. |
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